shortened CRC

用法例句

Research on the kind of shortened CRC from math theory and matlab emulator is described,and the internal relation between the polynomial and the coding checkout capability illustrated in this paper.

在此基础上对应用广泛的一类缩短循环码的校验性能从数学理论和matlab仿真模型两方面进行研究,更直观的揭示了生成多项式与编码校验性能的内在联系,为构造更优化的标准打下基础。

Furthermore,according to the basic algorithm steps of BM,the practical shortened code(50,32)is analyzed through the three-stage pipeline algorithm architecture.

根据BM迭代译码算法的基本步骤,采用三级流水算法结构并对实际应用的缩短码(50,32)(纠二检四)译码进行分析,同时阐明如何应用C/C++语言实现该算法。

Short-cycle Software System of WEDM;

线切割机床的贮丝筒短循环软件系统

The Software Realization of Shortened Cycle Code(26,16) Encoding and Decoding

缩短循环码(26,16)编码和译码的软件实现

Research on Cyclic Code and Constacyclic Code over Ring F_2+uF_2;

环F_2+uF_2上的循环码和常循环码的研究

The Binary Image of K-Cyclic Code, Cyclic Code and Quasi-Cyclic Code over Z_4;

环Z_4上的K-循环码，循环码和准循环码的二进制像

(1+u~k) constacyclic codes over F_2+uF_2+…+u~kF_2

环F_2+uF_2+…+u~kF_2上的循环码和(1+u~k)循环码

A Coding and Decoding Algorithm and its implementation of shortened BCH Codes(16,8,5)

缩短BCH码(16,8,5)编译码算法及其实现

multi-stage compression refrigeration cycle

多级压缩式制冷循环

Construction of QC-LDPC Codes based on Cyclic Groups

基于循环群的准循环LDPC码构造

Cyclic Codes and Quadratic Residue Codes over Ring F_2+uF_2;

环F_2+uF_2上的循环码和二次剩余码

Dual Codes of Cyclic Codes over Ring F_2+uF_2 of Length 2~e;

环F_2+uF_2上2~e长循环码的对偶码

CP-to-binary code converter

循环排列码－二进制码转换器

FPGA Decoder Implementation for Quasi-Cyclic Low-Density Parity-Check Codes;

准循环低密度校验码译码器的FPGA实现

Research on Decoding Tech of Convolutional Turbo Codes;

循环卷积Turbo码译码技术研究

Design of Codec for Quasi-cyclic LDPC Codes and Its FPGA Implementation

准循环LDPC码的编译码器设计及FPGA实现

Tail-biting Decoding of Circular Recursive Systematic Turbo Code in DVB-RCS

DVB-RCS中循环递归Turbo码尾比特译码技术

Symbol Based Circular State Turbo Code and its Decoder

基于符号的循环状态Turbo码及其解码器

Construction of Quasi-Cyclic LDPC Block and Convolutional Codes

准循环LDPC分组码和卷积码的构造

An 800Mbps Quasi-Cyclic LDPC Encoder Implementation with FPGA

800Mbps准循环LDPC码编码器的FPGA实现

An FPGA Implementation of QC-LDPC Decoder

准循环LDPC码译码器的FPGA实现